1. Field of the Invention
This invention relates to a data storing device, more specifically the data storing device having a plurality of memory cells including a first switch and a second switch, each of which shows different switching states.
2. Description of the Related Art
A static random access memory (hereinafter referred to as SRAM) using a metal oxide semiconductor field effect transistor (hereinafter referred to as MOSFET) is known as a data storing device. FIG. 14 is a circuit diagram illustrating an example of a memory cell composing an SRAM in the prior art.
A memory cell MC comprises a pair of transistors MT1 and MT2 for storing data (hereinafter referred to as memory transistors), and a pair of resistors R1 and R2. Also, the memory cell MC is connected to a pair of bit lines BL and BLB (both of the lines are referred to as bit lines pair BLP) through a pair of selector transistors ST1 and ST2 (both the transistors are referred to as selector transistors pair STP). Gate electrodes of the selector transistors pair STP are connected to a word line WL. A plurality of the memory cells MC are arranged within the SRAM in a matrix format.
In order to store a data into a memory cell in the SRAM, a voltage corresponding to the data to be stored therein is applied to the bit lines pair BLP. For example, both voltages representing "LOW" and "HIGH" are applied to the bit line BL and the bit line BLB respectively when data "0" is stored in the memory cell MC.
Then, the selector transistors pair STP is turned into ON state by applying a voltage representing "HIGH" to the word line WL. As a result, the memory transistor MT1 is in ON state while the memory transistor MT2 is in OFF state. Thus, the data "0" is stored in the memory cell MC. In order to store data "1" in the memory cell MC, voltages opposite to the previous such as the voltages representing "HIGH" and "LOW" may be applied to the bit line BL and the bit line BLB respectively.
Thereafter, the memory cell MC is turned into stand-by state by making the selector transistors pair STP into OFF state as a result of applying a voltage representing "LOW" to the word line WL. The data stored in the memory cell MC is remained as it is even when the memory cell MC is in the stand-by state as a result of a function so called "self-latching up" which is owned by the memory cell MC.
In order to read out the data stored in the memory cell MC, the selector transistors pair STP is turned into ON state by applying the voltage representing "HIGH" to the word line WL, and the voltages existing on the bit lines pair BLP are detected. In this way, the data stored in the memory cell MC can be detected.
However, the SRAM has the following problems to be resolved. In the SRAM described above, a voltage for maintaining the data stored therein need to be applied to the circuit all the time. A power supply just for maintaining the data is required even when neither storing nor reading the data are carried out. Therefore, unnecessary power is consumed under a condition that carries out no data storing and no data reading. Further, the data stored in the memory cell MC may be erased when the power source is out of order by an accident or other reasons.
Although, the use of an electrically erasable programmable read only memory (hereinafter referred to as EEPROM) would help to resolve the problem stated above, the EEPROM requiring a long time for storing the data is not suitable for a data storing device requiring high-speed responses. In addition, high voltages (for example voltages above 12 volts) are required for storing and erasing the data in the EEPROM. Therefore, either of a step-up transformer disposed on a chip or an additional power supply for high voltages beside the regular power supply is needed so that the chip having compactness as well as lower manufacturing cost can not be achieved.